wafer manufacturing 結果共4筆

Discover Taiwan’s ambitious plan to become an AI powerhouse, unveiled by President Lai at Taipei COMPUTEX. With support from NVIDIA and TSMC, the initiative focuses on stable power, supercomputers, and talent in AI and semiconductors.

Taiwan Semiconductor Manufacturing Company (TSMC) has announced that its Japan subsidiary, JASM, will construct a second wafer fabrication plant by the end of 2024. The plant is expected to be operational by the end of 2027. With support from the Japanese government, TSMC plans to begin production at its first JASM wafer fabrication plant in 2024, with a total investment exceeding US＄20 billion. The construction of the second plant is driven by increasing customer demand. The expansion aims to optimize JASM’s cost structure and supply chain efficiency, resulting in increased production. Once both plants are operational, JASM’s Kumamoto wafer fabrication plant will have a monthly capacity of over 100,000 12-inch wafers. The Japan fab will offer process technologies ranging from 40nm to 6nm, catering to automotive, industrial, consumer, and high-performance computing applications. TSMC also mentioned that capacity planning can be adjusted based on client requirements. The Kumamoto wafer plant is expected to create more than 3,400 high-tech professional jobs.

Taiwan Semiconductor Manufacturing Company (TSMC) predicts a surge in artificial intelligence (AI) orders in the coming year, with October’s revenue reaching NT$243.203 billion ($8.6 billion), a 34.8 percent monthly increase and a 15.7 percent annual increase. TSMC’s stock price has also been on a steady rise, accumulating a growth of 7.5 percent since November. Morgan Stanley semiconductor research analyst Charlie Chan attributes TSMC’s revenue growth to signs of recovery and the robust demand for AI semiconductors worldwide. NVIDIA’s expanded order to TSMC, along with increased demand from clients like Apple and Advanced Micro Devices (AMD), has led TSMC to accelerate the enhancement of its advanced packaging technology, Chip on Wafer on Substrate (CoWoS). CoWoS enables TSMC to effectively reduce costs and trim electric consumption by packaging chiplets on a silicon interposer and placing them on a package substrate. However, TSMC’s current CoWoS capacity remains a bottleneck for NVIDIA’s AI GPU chips, though the company forecasts a rebound in productivity by the end of 2024 to meet customer demand.

The total semiconductor industry output is projected to reach NT＄4.3 trillion in 2023, with a year-on-year decrease of 11.2%, according to a revised forecast by Taiwan’s Industrial Technology Investment Corporation (ITRI). The wafer foundry industry is expected to have an output value of NT＄2.46 trillion, surpassing the earlier forecast of NT＄2.38 trillion, and showing an 8.2% yearly decrease. The semiconductor manufacturing industry, including wafer foundry and DRAM, is set to have an output value of NT＄2.64 trillion, with a year-on-year decrease of 9.6%. TSMC’s operational growth is likely to contribute to an anticipated 8.1% growth in Taiwan’s semiconductor manufacturing output in the fourth quarter.